Efficient MVL Circuit Design with Use of p-CNTFETs and n-CNTFETs

As the miniaturization of silicon based circuits reaches its physical limits, the exigency of substitute technologies emerges. Special characteristics of CNT such as high mobility of electrons, ballistic transport and high Ion-Ioff ratio, has introduced it as an appropriate successor to silicon MOSFET. Whereas the threshold voltage cannot be decreased deliberately due to the scaling limitations of MOSFETs, in CNTFETs different threshold voltages can be obtained simply by defining different nanotube diameters because the threshold voltage is in reverse proportion with the nanotube diameter [1]. This feature of carbon nanotubes has been exploited in implementation of multiple valued logic (MVL) circuits. One of the principal ways in MVL circuit implementation is by using basic operators such as tsum, literal, min and max. In [2] we introduced a new approach for ternary Galois field design that employed different paths to obtain different logic levels and showed that this approach is more efficient than using basic MVL operators. In [3] we presented another design for Galois field which employed sharing paths method to obtain output logical levels. In this paper we propose a CNTFET design for multiplication and addition circuits that not only take advantages of these two but also further reduces the number of transistors by the idea of bridging a resistor between CNTFETs.